Most of the power and usefulness of today's digital IC devices can be attributed to the increasing levels of integration. More and more components (resistors, diodes, transistors, and the like) are continually being integrated into the underlying chip, or IC. The starting material for typical ICs is very high purity silicon. The material is grown as a single crystal. It takes the shape of a solid cylinder. This crystal is then sawed (like a loaf of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
The geometry of the features of the IC components are commonly defined photographically through a process known as photolithography. Very fine surface geometries can be reproduced accurately using this technique. The photolithography process is used to define component regions and build up electronic components one layer on top of another. Complex ICs can often have many different built up layers, each layer having numerous electronic components, each layer having differing interconnections, and each layer stacked on top of the previous layer. The resulting topography of these complex IC's often resemble familiar terrestrial "mountain ranges", with many "hills" and "valleys" as the components are built up on the underlying surface.
In the photolithography process, a mask image, or pattern, defining the various components, is focused onto a photosensitive layer using ultraviolet light. The image is focused onto the surface using the optical means of the photolithography tool, and is imprinted into the photosensitive layer. To build ever smaller features, increasingly fine images must be focused onto the surface of the photosensitive layer, i.e. optical resolution must increase. As optical resolution increases, the depth of focus of the mask image correspondingly narrows. This is due to the narrow range in depth of focus imposed by the high numerical aperture lenses in the photolithography tool. This narrowing depth of focus is often the limiting factor in the degree of resolution obtainable, and thus, the smallest components obtainable using the photolithography tool. The extreme topography of complex ICs, the "hills" and "valleys," exaggerate the effects of decreasing depth of focus. Thus, in order to properly focus the mask image defining sub-micron geometries onto the photosensitive layer, a precisely flat surface is desired. The precisely flat (i.e. fully planarized) surface will allow for extremely small depths of focus, which in turn, allows the definition and subsequent fabrication of extremely small components.
Chemical-mechanical polishing (CMP) is the preferred method of obtaining full planarization of a wafer. It involves removing a sacrificial layer of dielectric material using mechanical contact between the wafer and a moving polishing pad saturated with slurry. Polishing flattens out height differences, since areas of high topography (hills) are removed faster than areas of low topography (valleys).
Prior Art FIG. 1A shows a top view of a CMP machine 100 and Prior Art FIG. 1B shows a side section view of the CMP machine 100 taken through line AA. CMP machine 100 is fed wafers to be polished. CMP machine 100 picks up the wafers with an arm 101 and places them onto a rotating polishing pad 102. Polishing pad 102 is made of a resilient material and is textured, often with a plurality of predetermined groves, to aid the polishing process. Polishing pad 102 rotates on a platen 104, or turn table located beneath polishing pad 102, at a predetermined speed. A wafer 105 is held in place on polishing pad 102 by arm 101. The lower surface of wafer 105 rests against polishing pad 102. The upper surface of wafer 105 is against the lower surface of a wafer carrier 106 of arm 101. As polishing pad 102 rotates, arm 101 rotates wafer 105 at a predetermined rate. Arm 101 forces wafer 105 into polishing pad 102 with a predetermined amount of down force. CMP machine 100 also includes a slurry dispense arm 107 extending across the radius of polishing pad 102. Slurry dispense arm 107 dispenses a flow of slurry onto polishing pad 102.
CMP is increasingly being used for planarizing dielectrics and other layers, particularly for applications using 0.35 .mu.m and smaller semiconductor fabrication processes. Effective CMP planarization techniques have led to the fabrication of many complex multi-layer electronic components. Electronic interconnections are built into the components to interconnect the circuits on differing layers. These interconnections include structures referred to as "plugs", and are typically fabricated using tungsten. For the reasons described above (e.g., lithography), the underlying dielectric layer needs to be planarized prior to subsequent fabrication processing.
CMP is widely accepted as the preferred process for planarizing tungsten plugs, particularly for the emerging field of 0.25 .mu.m and below fabrication technologies. In accordance with prior art CMP processes, an oxide layer of a component is etched to include openings for vias and plugs. An overlying layer of tungsten is subsequently deposited onto the oxide layer and the openings are filled with tungsten. The overlying tungsten layer is then removed from the underlying oxide surface such that after removal, tungsten is only present within the plugs. The tungsten is removed down to the underlying dielectric surface. The underlying dielectric surface in which the tungsten plugs are formed is partially planarized using a spin-on glass etchback process. Prior to tungsten deposition, the oxide surface is at least partially planarized to aid lithography. There is a problem, however, in that tungsten CMP in accordance with the prior art is regarded as being incompatible with widely used partial planarization techniques (e.g., spin-on glass etchback).
Prior Art FIG. 2A shows a portion of a semiconductor component 200. Component 200 includes an overlying tungsten layer 201, an underlying dielectric layer 202, an underlying metal line 203, and an underlying metal line 205. A tungsten plug 204 is formed prom the tungsten layer 201. The surface of underlying layer 202 includes a groove 206.
Tungsten plug 204 is formed by etching an opening in dielectric layer 202 and subsequently depositing tungsten layer 201. Tungsten is deposited across the surface of component 200. In the process, the openings, grooves, etched patterns, and the like, across the surface are filled in by tungsten layer 201. In the process, tungsten plug 204 is filled, along with a groove 206. Groove 206 is an inadvertent by-product of the spin-on-glass (SOG) etchback planarization technique.
SOG etchback is a widely used and well known technique for depositing dielectric layers and then partially planarizing them. Although SOG etchback is widely used, it does not provide the global planarity obtained with the more recent CMP techniques. However, since SOG etchback is very well known, it is still widely used within the semiconductor fabrication industry for depositing and partially planarizing dielectric layers (e.g., dielectric layer 202). Hence, dielectric layer 202 is deposited and partially planarized using an SOG etchback process, leaving behind groove 206. Dielectric layer 202 is then covered with tungsten layer 201, as described above.
Prior Art FIG. 2B shows component 200 after a prior art CMP process. The SOG etchback process leaves behind groove 206 in which tungsten layer 202 fills in. Surface 207 is the planarized surface of component 200 after the prior art CMP process. Thus, even after the prior art CMP process, tungsten remains within groove 206. This results in "stringers" which can lead to electrical shorts between the patterned metal circuits of component 200, or other such defects.
Additionally, in a typical prior art CMP process, the thickness of the underlying dielectric layer (e.g., dielectric layer 202) needs to be closely controlled. As such, it is expected that the underlying dielectric layer will have very little material removed. The prior art CMP process is adjusted to remove more tungsten than dielectric material (e.g., a high selectivity of tungsten in relation to oxide is used). However, the high selectivity of tungsten is unable to solve the problems posed by planarity defects such as groove 206. As a result, CMP in accordance with the prior art is widely considered incompatible with the partial planarization techniques used in typical tungsten component fabrication technology.
Thus, what is required is a system which improves the performance of the tungsten CMP process and is still compatible with the partial planarization techniques used in tungsten component fabrication. The required solution should provide a planarization process which can be utilized subsequent to tungsten deposition on a partially planarized surface. The required solution should be compatible with partial planarization techniques (e.g., SOG and the like) and not lead to the formation of component surface defects such as stringers and shorted circuits. The present invention provides a novel solution to the above requirements.